The microelectronics industry is highly competitive and microelectronics manufacturers are very sensitive to quality and cost considerations. Most microelectronics manufacturers require that suppliers of microelectronic components test the performance of each microelectronic component before shipment to minimize the manufacturer's product losses. For example, microelectronic imagers are commonly tested by establishing temporary electrical connections between a test system and electrical contacts on each microelectronic imaging die while simultaneously exposing an image sensor on the device to light.
One way of establishing a temporary electrical connection between the test system and the contacts on a microelectronic component employs a probe card carrying a plurality of probe pins. The probe pins are typically either a length of wire (e.g., cantilevered wire probes) or a relatively complex spring-biased mechanism (e.g., pogo pins). The probe pins are connected to the probe card and arranged in a predetermined array for use with a specific microelectronic component configuration. For example, when testing a microelectronic imager with a conventional probe card (whether it be a cantilevered wire probe card, a pogo pin probe card, or another design), the probe card is positioned proximate to the front side of the imaging die to be tested. The probe card and the imaging die are aligned with each other in an effort to precisely align each of the probe pins of the probe card with a corresponding electrical contact of the front side of the imaging die.
One problem with testing imaging dies at the wafer level is that it is difficult to expose an image sensor to light while simultaneously aligning the probe pins or the body of the probe card with the corresponding electrical contacts on the front side of the imaging die. For example, because the probe card is positioned over the image sensor to contact the front side bond-pads on the die, the probe card must have a plurality of holes or apertures through which light can pass. This limits wafer-level testing methods because the physical constraints of probe card structures and the limited testing area available on the wafer. Further, the probe card and/or probe pins positioned proximate (but not over) the image sensor also interfere with the light directed to the image sensor (e.g., shadowing, reflections). These limitations result in the ability to test only a fraction of the imaging dies on a wafer of imaging dies as compared to the number of other types of dies that can be tested in non-imaging applications (e.g., memory, processors, etc.). For example, only four CMOS imaging dies can be tested simultaneously on a wafer compared to 128 DRAM dies using the same equipment. Accordingly, there is a need to improve the efficiency and throughput for testing imaging dies.
Another problem with conventional probe card testing methods is that the testing process can introduce moisture and/or other contaminants to the image sensors. For example, conventional probe cards and/or probe pins are positioned over the image sensors to contact the bond-pads on the front side of the dies. Accordingly, tiny particles generated during the testing process or otherwise on the probe pins can fall onto the image sensors. This can cause a malfunction or failure because a particle as small as ten microns can effectively ruin an image sensor. Accordingly, there is a further need to improve the testing of imaging dies.